1. Field of the Invention
The present invention relates to a multiplex switching circuit and a multiplex switching method for multiplexing input packets on a plurality of channels for switching in a base station or the like of a W-CDMA (Wideband-Code Division Multiple Access) radio communications system.
2. Description of the Related Art
Conventionally, in radio communications systems such as a digital portable telephone, a packet transmission apparatus for transmitting packets on a plurality of channels is required to provide high throughput performance for processing a larger amount of small packets supplied thereto at a lower cost. However, when an increased number of channels are supplied at the same time, if a burst of input packets occurs, the packets will stagnate in an internal RAM (buffer) which is used for temporarily storing input packets. Then, when the stagnation of packets results in a scarcity of RAM area, packets can no longer be stored in the internal RAM, possibly causing a delay in processing, buffer overflow, and the like.
As illustrated in FIG. 1, in a conventional packet transmission apparatus, packets on a plurality of channels are multiplexed and stored in RAM 601 provided within the packet transmission apparatus. Thus, when packets are supplied to each channel in a bursty manner, the packets will stagnate in RAM 601 because output processing cannot keep up with packets supplied into RAM 601 if attention is paid to a certain time.
For this reason, the conventional packet transmission apparatus is required to have a large-capacity storage area for storing packets in the event that loads are concentrated in a network having a large number of input and output channels co-exist. If the capacity of RAM can be increased for use as a storage area, packets can be stored therein even if a burst of input packets occurs.
However, it is difficult to infinitely increase the capacity of RAM due to the limitations of price, circuit scale and the like of devices.
On the other hand, if the output throughput can be increased, packets can be sent out without stagnating in internal RAM, thus eliminating the need for increasing the capacity of internal RAM. However, since the output throughput is determined based on the operation frequency of an internal circuit, it is difficult to infinitely increase the output throughput due to limitations in the operation frequency.
To address the foregoing problem, JP2005-020609A discloses a method for managing the storage area of memory in order to temporarily store data in an apparatus connected to a network, and in order to limit input data when free capacity is reduced in the storage area.
However, although the method disclosed in the foregoing patent document can solve the problem of packet data overflow in the apparatus, there is still a problem that packet data will stagnate in the preceding apparatus, so that the capacity of RAM must be increased in the preceding apparatus. In addition, since the location in which packet data is stored simply moves from the apparatus of interest to the preceding apparatus, the disclosed method fails to solve a problem of eliminating a delay in data transmission.